FPGA computing systems: Partial Dynamic Reconfiguration

New application domains demand ever increasing adaptability and performance. In order to cope with changing user requirements, improvements in system features, changing protocol and data-coding standards, and demands for support of a variety of different user applications, many emerging applications in communication, computing and consumer electronics demand that their functionality stays flexible after the system has been manufactured. Reconfigurable Systems-on-a-Chips (SoCs) employing different microprocessor cores and different types of reconfigurable fabrics are one attractive solution for these domains. The increasing prominence of reconfigurable devices within such systems requires HW/SW co-design for SoCs to address the trade-off between software execution and reconfigurable hardware acceleration. Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain. During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration.   The course will introduce the student with the concept of reconfigurability in FPGAs, presenting the available mechanisms and technologies at the device level and the tools and design methodologies required to design reconfigurable FPGA-based systems. The course will present the different aspects of the design of FPGA-based reconfigurable systems, focusing in particular on dynamically self-reconfigurable systems. The design methodologies and tools required to design a dynamically-reconfigurable system will be introduced and described, together with the problems that need to be considered.